Разработка и аппаратная реализация декодера помехоустойчивого полиномиального кода (15, 8, 3), исправляющего пакетные ошибки, на ПЛИС

Abstract

This article presents the structure, on which based the implementation of highspeed error-correcting decoder by polynomial code, which can correct burst errors, based on the cyclic decoding algorithm. In order to increase the decoder performance, a series circuit has been replaced by the combination. In addition to implementation, decoder was tested to confirm its efficiency in finding and correcting the burst errors, which can reach three consecutive bits. Also, in order to ensure its performance, was carried out comparative analysis of the combinational circuit and decoder, correcting the same number of errors, but with the memory elements. A comparative analysis clearly received confirmation of the decoder performance, built on combinational logic circuits without using of memory elements.